Thyristor turn-off system

ABSTRACT

A thyristor turn-off system comprising: a thyristor having at least an anode, a cathode and a gate; a first reverse-bias means for applying reverse-bias between said anode and said cathode of the thyristor; a second reverse-bias means for applying reverse-bias to said gate of the thryistor; means for applying reverse-bias to said gate of the thyristor by said second reverse-bias means during the time of or before or after the forward bias initiation time for shifting between said anode and said cathode of the thyristor from reverse-bias to forward bias; whereby a failure of turn-off of the thyristor is prevented by said gate reverse-bias at least after said forward bias initiation time.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation-In-Part of U.S. application Ser. No.545,906, filed Jan. 31, 1975, and now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a thyristor turn-off system forshortening the turn-off period and simplifying the turn-off means.

2. Description of the Prior Art

As is known, a turn-off of the conventional thyristor has been performedby reverse-biasing between an anode and a cathode for a specific period.According to the conventional turn-off system, a turn-off period mustusually be greater than 10 μ sec.. It has been difficult to shorten theturn-off period for a current thyristor of higher than 50 A or a highvoltage thyristor, for example, higher than 800 V. Accordingly,complicated turn-off means has been required and the loss for theturn-off has been large. The disadvantages have been great in the caseof high frequency switching.

As is known in the conventional gate turn-off thyristor, the thyristoris turned off by reverse-biasing the gate. It has been hard to use thegate turn-off thyristor for large current such as greater than 10 A orfor high voltage such as higher than 600 V. On the other hand, it hasbeen difficult to use a transistor for current of greater than about 30A and high voltage of higher than 300 V. Even though the static breakover voltage V_(ceo) or V_(cbo) can be higher than 300 V, it has beendifficult to use it for high speed high frequency switching because ofthe break down by switching power.

An allowable surge current of a transistor is smaller than that of athyristor. Accordingly, it is not feasible to use a transistor for ahigh power switching purpose. Accordingly, it has not been possible toovercome the disadvantages of a thyristor by a transistor.

SUMMARY OF THE INVENTION

The present invention is to overcome the disadvantages of theconventional power switching elements.

It is an object of the present invention to provide a thyristor turn-offsystem for decreasing the turn-off period of the thyristor, simplifyingthe turn-off means and decreasing the loss required for the gatereverse-bias by reverse-biasing between the anode and cathode of thethyristor and reverse-biasing the gate thereof.

The foregoing and other objects are attained in accordance with oneaspect of the present invention, through the provision of a thyristorturn-off system comprising: a thyristor having at least an anode, acathode and a gate; a first reverse-bias means for applying reverse-biasbetween said anode and said cathode of the thyristor; a secondreverse-bias means for applying reverse-bias to said gate of thethyristor; means for applying reverse-bias to said gate of the thyristorby said second reverse-bias means during the time of or before or afterthe forward bias initiation time for shifting between said anode andsaid cathode of the thyristor from reverse-bias to forward bias; wherebya failure of turn-off of the thyristor is prevented by said gatereverse-bias at least after said forward bias initiation time.

BRIEF DESCRIPTION OF THE DRAWINGS

Various objects, features and attendant advantages of the presentinvention will be more fully appreciated as the same becomes betterunderstood from the following detailed description of the presentinvention when considered in connection with the accompanying drawings,in which:

FIG. 1 is a connection diagram for illustrating one embodiment of thethyristor turn-off system according to the invention;

FIG. 2, a-c, and FIG. 3, a-j, are waveforms for illustrating theoperation of the system;

FIGS. 4a, 4b and 4c are diagrams of a conceptual circuit model forillustrating the operation of the system;

FIG. 5a is a side view of a cathode for illustrating a schematicstructure of a suitable thyristor element for applying the thyristorturn-off system;

FIG. 5b is a sectional view taken along the line X -- X of FIG. 5a;

FIG. 6 is a connection diagram of the first embodiment of the thyristorturn-off system according to the invention;

FIG. 7, a-c, shows waveforms for illustrating the operation of thesystem of FIG. 6.

FIG. 8 is a circuit diagram of the second embodiment of the thyristorturn-off system according to the invention;

FIG. 9, a and b, shows time charts of waveforms for illustrating theoperation of the system of FIG. 8;

FIG. 10 is a connection diagram of the third embodiment of the thyristorturn-off system according to the invention;

FIG. 11, a and b, shows time charts of waveforms for illustrating theoperation of the system of FIG. 10;

FIG. 12 is a simplified block diagram for the circuit diagrams of FIGS.8 and 10;

FIG. 13 and FIG. 14 are circuit diagrams for the fourth and fifthembodiments of the thyristor turn-off system according to the invention;

FIG. 15 is a simplified block diagram for illustrating circuit diagramsof FIGS. 13 and 14;

FIG. 16 is a connection diagram of the sixth embodiment of the thyristorturn-off system according to the invention; FIG. 17, a-c, showswaveforms for illustrating the operation of the system of FIG. 16;

FIG. 18 and FIG. 19 are circuit diagrams for applications of thethyristor turn-off system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the drawings, wherein like reference numerals designateidentical or corresponding parts throughout the several views, and moreparticularly to FIG. 1 thereof;

FIG. 1 is a connection diagram for illustrating the thyristor turn-offsystem of the invention wherein a load 2 and a thyristor 3 are connectedin series between positive and negative poles of a DC power source 1. Aseries circuit of an anode reverse bias power source 4 and an anodereverse-bias switch 5 is connected in parallel to the thyristor 3 so asto form the first reverse-bias means 7 consisting of the anodereverse-bias power source 4 and the anode reverse-bias switch 5. Theanode reverse-bias power source 4 can be replaced by an anodereverse-bias capacitor 4a as shown by the dotted line. The secondreverse-bias means 8 is to reverse-bias the gate of thyristor 3, and isconnected to the gate and cathode of the thyristor 3.

Referring to FIG. 2, a-c, the operation of the system will beillustrated. At the time t₁, the turn-on pulse i_(gf) is applied to thegate of thyristor 3 as shown in FIG. 2c so as to turn on the thyristor3, whereby the forward current i_(af) shown in FIG. 2b is passed to thethyristor 3. During the period, the voltage V₃ of the thyristor 3 isonly the forward voltage drop as shown in FIG. 2a. When the thyristor 3is turned off, the anode reverse-bias switch 5 is turned on whereby theanode reverse-bias voltage V_(ar) (FIG. 2a) is applied to the anode ofthyristor 3 by the first reverse-bias means 7 from the time t₂ to t₄.Then, at the time t₅, the voltage of the thyristor reaches normalforward voltage V_(af). The period t₄ - t₅ is a transient restrikingforward voltage increase period. The period t₂ - t₄ is an anodereverse-bias period t_(ar).

On the other hand, as stated above, the reverse current i_(ar) (FIG. 2b)is fed from the time t₂ as the current i₃ of the thyristor 3 by applyinga reverse-bias voltage to the anode of the thyristor 3 so as todischarge the stored carriers. The anode reverse-bias is stopped fromthe time t₃ - t₄ when the discharge of the stored carriers issubstantially finished and the reverse current i_(ar) is substantiallyzero. Then, the forward voltage begins to apply and the gatereverse-bias current i_(gr) begins to feed to the gate of thyristor 3 bythe second reverse-bias means 8 at the time t₃ between the period t₂ -t₄. The period t₃ - t₄ is an overlapping period t_(u) (FIG. 2c) for theanode reverse-bias and the gate reverse-bias. It is, of course,preferable to have an overlapping period t_(u). However, it is notindispensable and it is possible to have t_(u) = 0 or t_(u) < 0 and t₃ >t₄. That is, the preliminary result of the invention can be attained byapplying the gate reverse-bias at the time of passing the zero pointfrom the finish of the anode reverse-bias to the forward voltage t₄ (t₃= t₄, t_(u) = 0) or at the time delaying a certain period t_(d) (delaytime for breakover as the junction J₂ is not sufficiently recovered;such as several μ sec. - several tens μ sec.). An object of theinvention, to be illustrated later, is to prevent the failure ofturn-off by break-over after a certain delay) from the blocking of theforward voltage once in the condition of incomplete recovery of thejunction J₂.

In order to illustrate the problem, the waveform of the voltage V₃ ofthe thyristor 3 is shown in FIG. 3a, and the time relations of the gatereverse-bias are shown in FIG. 3, b-j. FIGS. 3, b and c, shows applyingthe gate reverse-bias during the period including the forward biasinitiation time t₄. FIGS. 3, d and e, shows applying the gatereverse-bias just after the forward-bias initiation time t₄. FIG. 3fshows applying the gate reverse-bias after delay of the time t_(d) fromthe time t₄. FIG. 3g shows applying the gate reverse-bias before andafter the forward-bias initiation time t₄. FIG. 3, h-j, shows applyinggate reverse-bias by the pulse-train corresponding to FIGS. 3, b, c andf.

The breakover after the reapplication of the forward voltage can becaused after a certain delay in many cases. Accordingly, the result ofpreventing the breakover can be expected even by application of thereverse-bias by the pulse train. In accordance with the pulse trainreverse-bias system, the main circuit and the insulation (pulsetransformer, etc.) as the gate reverse-bias means can be miniaturized.The common feature is to apply the gate reverse-bias after the forwardvoltage initiation time t₄ and at least before the breakover delay timet_(d). This is the first feature of the invention.

One of the more important features of the invention is to continuouslyapply the gate reverse-bias even after the finish of the anodereverse-bias (after restriking the forward voltage initiation time t₄)until the time t₆. The gate reverse-bias period t_(gr) occurs during theperiod t₃ - t₆. Another feature of the invention is to graduallydecrease the reverse-bias current after applying the forward voltage.The feature will be illustrated later.

FIGS. 4a, 4b and 4c are equivalent circuit diagrams showing theconnection in each period to the time charts of the waveforms of FIG. 2,a-c. In FIGS. 4a, 4b and 4c the thyristor 3 has a PNPN four layerstructure and has an anode A, a cathode K, and a gate G. FIGS. 4a, 4band 4c show the cathode side gate (P gate). (In the case of the anodeside gate (N gate), a gate electrode is provided in the first N layer(N₁)).

The P gate type thyristor will now be described. In the case of FIG. 4a,only the anode reverse-bias voltage V_(ar) is applied during the periodt₂ - t₃ of FIG. 2, a-c. During the period, the carriers around thejunctions J₁, J₃ are discharged by the reverse current i_(ar). When thecarriers around the junctions J₁, J₃ are discharged, the reverse voltageis maintained by the junction J₂ to prevent the discharge. However, thecarriers around the junction J₂ still remain and the forward voltageblocking ability is not recovered until the completion of recombination.(In the conventional turn-off using only the anode reverse-bias, theperiod for completion of the recombination is too long, and issubstantially the turn-off time).

FIG. 4b shows the connection mode during the overlapping period t_(u)for the period t₃ - t₄. In this case, it is possible to have t₂ = t₃,that is, to apply simultaneously the anode reverse-bias and the gatereverse-bias. In the state of FIG. 4b, the discharge of the remainingcarriers around the junctions J₂, J₃ continues from anode reverse-biasV_(ar). In FIG. 4a, the small number of remaining carriers around thejunctions J₁, J₃ are discharged. On the other hand, a large number ofremaining carriers around the junction J₂ is discharged by the gatereverse-bias i_(gr).

However, in the case of t₂ = t₃, that is the simultaneous application ofthe anode reverse-bias and the gate reverse-bias from the beginning,(applying the gate reverse-bias at the time a large number of carriersremains around the junctions J₁, J₃ to pass the reverse current i_(ar)and at the time recovering insufficient reverse-blocking ability), thejunction J₂ is forwardly biased by the anode reverse-current i_(ar) bythe anode reverse-bias whereby the discharge of carriers around thejunction J₂ as the purpose of the gate reverse-bias (the recovery ofblocking ability of the junction J₂) is prevented. The junction J₂ isforwardly biased around the gate electrode by the loop of cathodeterminal K-second reverse bias means 8-gate electrode G-second P layerP₂ -first N layer N₁ -first P layer P₁ -anode electrode A-firstreverse-bias means 7.

The gate current i_(g) can be forwardly passed by overcoming the secondreverse-bias means 8. It is immaterial whether the gate reverse-bias isapplied before the recovery of the junctions J₁, J₃, that is, beforesufficient decrease of the anode reverse current i_(ar). This causesloss of the gate reverse-bias circuit. That is, the optimum method is toapply the gate reverse-bias after sufficient decrease of the anodereverse current i_(ar). The delay feature of the gate reverse-bias timet₃ from the anode reverse-bias initiation time t₂ is one of the featuresof the invention. After the anode reverse current i_(ar) by the anodereverse-bias is satisfactorily decreased in the mode of FIG. 4b, andafter the reverse current blocking ability of the junctions J₁, J₃ issufficiently recovered, a large number of the remaining carriers aroundthe junction J₂ by the gate reverse-bias current are discharged. Thejunction J₂ will be recovered.

When the junction J₁ is recovered and the shared voltage V_(J1) of thereverse voltage of the junction J₁ reaches higher than the differencebetween the anode reverse voltage V_(ar) and the gate reverse voltageV_(gr) (that is to cause the potential of the N₁ layer at the junctionJ₂ surface region to be higher than the potential of the P₂ layer (gatelayer), the junction J₂ is reversely biased to obtain the reverserecovery (recovery of forward direction blocking ability). As isapparent from the description, the discharge and recovery of thecarriers of the junction J₂ by the gate reverse bias (recovery offorward direction blocking ability, that is, turn-off) is highlydependent upon the recovery of the junction J₁ layer by the anodereverse-bias. But, from the viewpoint of the gate reverse-bias (recoveryof junction J₂), the anode reverse-bias is forwardly biasing thejunction J₂ and is disturbing the recovery of the junction J₂. This is adisadvantage compared to the case of the gate reverse-bias as V_(ar) =0. Accordingly, it is the optimum that the junction J₂ is recovered byapplying the gate reverse-bias during the period for the resultingnearly zero of the anode reverse-bias voltage after sufficient decreaseof the reverse current i_(ar) in FIG. 2b (after the time t₃).

It is also preferable to apply the gate reverse-bias during the periodthat the voltage between the anode and cathode V₃ (absolute value) islower than the gate reverse-bias voltage V_(gr) (period for (V_(gr) -|V₃ |) > 0) which is prolonged by the slow change from the reversevoltage to the forward voltage. Accordingly, it is effective to providethe reverse parallel diode 3a as shown in the dotted line as thethyristor 3 of FIG. 1. It is especially preferable to use a diode whoseturn-on is delayed from the time t_(r) for reverse direction recovery ora diode whose impedance is partially connected to an outer part or adiode whose forward voltage drop is relatively high.

The conventional turn-off method requires a large current to reversebias the gate or a long time for natural recombination of carriersaround junction J₂ because it is possible to only charge carriers aroundjunction J₂ by reverse anode current, and it is not possible todischarge carriers after the reverse anode current has nearly decreasedto zero, and the polarity of the electric field around junction J₂ isforward during t₂ - t₄. Accordingly, the gate reverse-bias is applieduntil after the forward voltage initiating time t₄. This is a primaryfeature of the invention. FIG. 4c shows the mode in the period of onlythe gate reverse-bias (t₄ - t₅) after the anode reverse-bias.

Referring to FIG. 4c, this feature will be described. The forwardrecovering current of the junction J₂ is derived as the gatereverse-bias current through the gate in the conditions that thejunction J₂ is not completely recovered and the forward leakage currentis greater than the normal forward leakage current whereby the amount ofthe carriers reaching the junction J₃ and fourth layer is decreased (orblocked) and the current amplification factor α₂ of the transistor of N₁-P₂ -N₂ is decreased (or operation stopped) so as to prevent breakover(forward direction turn-on). In order to prevent forward directionbreakover after decreasing the carriers, the anode reverse-biasingperiod (t₂ - t₄) takes quite a long time compared to the reverse currentperiod t_(r), in the conventional turn-off method. However, in thisinvention the period can be shortened by prolonging the gatereverse-bias period until after the forward voltage initiation wherebythe longest period for recombination of the turn-off interval of thethyristor can be eliminated. Moreover in comparison with only applyingthe reverse-bias current to the gate as the gate turn-on and offthyristor, the gate reverse-bias current can be quite small as it is thetime just after discharging a large number of carriers.

As illustrated in the mode of FIG. 4b, the gate reverse-bias has thedisadvantage in the mode whereby a satisfactory result cannot beexpected. In the forward direction blocking ability of the reapplicationof forward voltage in which a small number of remaining carriers isseriously affected, the effect of both reverse-biases is small as in thecase of FIG. 4b. On the contrary, the optimum result can be realized byprolonging the gate reverse-bias until after reapplication of theforward voltage. Without this feature, the result is substantiallysimilar to that of the case of turn-off by only anode reverse-bias orturn-off by only a gate reverse-bias. This is an important feature ofthe invention.

The following are detailed embodiments of the invention. FIG. 5a and 5b,show a thyristor for attaining the result of the invention, and are aschematic structure of the basic element.

FIG. 5a is a side view of the basic element in the cathode side, whereinthe slant lines portion of the radial pattern is a gate electrodesurface, and the margin is the cathode electrode surface and the fullline shows the boundary thereof.

FIG. 5b is a sectional schematic view taken along the line X--X of FIG.5a, wherein Ea (slant lines portion) designates an anode electrode; Ekdesignates a cathode electrode; and Pb designates a metallized electrodejointing layer for the anode, cathode and gate. The anode side P+ and Pdesignates the first P layer P₁ ; N designates the first N layer (baselayer) N₁ ; the next P designates the second P layer P₂ ; the gate sideP+ designates a gate layer; and the cathode side N+ designates thesecond N layer N₂. The gate region is smaller than that of theconventional gate turn-off thyristor. However, the suction of theforward leakage current to the gate and the disturbance of the currentamplification in the mode of FIG. 4c can be effectively attained byproviding a broad gate region such as that of the conventional gateturn-off thyristor.

FIG. 6 is a diagram of one embodiment for applying the gate reverse-biasaccording to the system of the invention wherein a load 2 and athyristor 3 are connected in series between the positive pole and thenegative pole of the DC power source; and the first reverse-bias means 7is connected between the anode and the cathode of the thyristor 3. Thesecond reverse-bias means 8 consists of the gate reverse-bias pulsegenerating means 10 and the gate reverse-bias gate circuit 20. The gatereverse-bias pulse generating means 10 comprises a gate reverse-biaspower source 41 and a gate reverse-bias switch 42. The gate reverse-biasgate circuit 20 comprises an inductive element 11 connected to the gateG of the thyristor and a gate reverse current wheeling diode 12.

FIG. 7, a-c, shows are time charts of turn-off waveforms in the circuitof FIG. 6. In FIG. 7a, V₃ and V₁₀₀ designate the voltage between themain electrodes of the thyristor 3. The anode reverse-bias is initiatedat the time t₂ and is finished at the time t₄. On the contrary, the gatereverse-bias pulse generation 10 generates the reverse voltage V₁₀ shownin FIG. 7b by the turn-on of the gate reverse-bias switch 42 during theperiod t₂ - t₅ wherein the time t₄ and t₅ can be slightly different.During the period the reverse pulse voltage V₁₀ is applied, the reversegate current i_(gr), that is, the current i₁₁ of the inductive element11 (FIG. 7c), increases to reach the maximum at the time t₅ (the timethe reverse bias voltage V₃ is extinguished). After the time t₅, thegate reverse current i_(gr) = i₁₁ is commutated to the diode and thereverse gate current is prolonged to the time t₅ by the effect of theinductive element 11 to gradually decrease to zero at the time t₆.

Thus, the large reverse gate current can be kept about the forwarddirection initiating time t₄ to impart the optimum gate reverse-biaseffect whereby the gate reverse-bias can be prolonged until after theapplication of the forward voltage for imparting the optimum forwarddirection blocking ability. The optimum gate reverse-bias means for theprinciple of the invention can thus be obtained. Even though the gatereverse-bias gate circuit 20 has no series resistance, the reverse gatecurrent can be decided by the inductive element 11 and the voltage-timeproduct of reverse pulse voltage V₁₀. With regard to the gatereverse-bias which requires a larger gate current than the turn-on gatecurrent, the gate reverse-bias power consumption can be greatlydecreased. Moreover, the inductive element 11 acts as a high impedanceto the application of the turn-on gate pulse so as to prevent a shunt ofthe turn-on gate current.

FIG. 8 is a diagram of another embodiment of the invention whichincludes the anode reverse-bias means. In the embodiment of FIG. 8, theanode reverse-bias means is used for both of the gate reverse-bias pulsegenerating means 10 of the embodiment of FIG. 6 and the firstreverse-bias means. In FIG. 8, the load 2 and the thyristor 3 areconnected in series between the positive terminal and the negativeterminal of the power source and the diode 9 is connected in parallel tothe load 2. The reference 4b in the first reverse-bias means 7 is aturn-off capacitor which is used instead of the anode reverse-bias powersource 4 in FIG. 1; an anode reverse-bias switch 5 is a turn-offthyristor in this embodiment. The series circuit of the turn-offcapacitor 4b and the anode reverse-bias switch 5 is connected inparallel to the thyristor 3. The series circuit of the diode 13 and thereactor 14 is connected in parallel to the anode reverse-bias switch 5whereby the first reverse-bias means 7 is formed. The series-connecteddiodes 12, 12a are connected in reverse polarity in parallel to thethyristor 3. The conjunction of the diodes 12, 12a is connected throughthe inductive element 11 to the gate of the thyristor 3 whereby the gatereverse-bias gate circuit 20 as shown by the dotted line is formed.

In FIG. 8, the turn-off capacitor 4b is charged through the anodereverse-bias switch 5 in the reverse polarity to that of FIG. 8 duringthe period of off state of the thyristor 3. When thyristor 3 is turnedon, the polarity is changed to that of FIG. 8 through the circuit ofreactor 14 - diode 13 - turn-off capacitor 4b - thyristor 3. Thethyristor 3 is thereby charged. In the case of the turn-off of thethyristor 3, the anode of the thyristor 3 is reversely biased by thevoltage of the turn-off capacitor 4b in the polarity of FIG. 8 when theturn-off thyristor 5, that is, the anode reverse-bias switch 5, isturned on at the time t₂. The anode reverse-voltage V₃ is applied as thegate reverse pulse voltage V₁₀ through the circuit of cathode K-gateG-inductive element 11 - diode 12a whereby the reverse gate currenti_(gr) is increased as shown by the waveforms during the period t₂ - t₄in FIG. 9, a and b. When the turn-off capacitor 4b is charged by theload current to the reverse polarity to that of FIG. 8, the anodevoltage V₃ is raised in the forward direction to rise to the voltage E₁of the power source 1. After the forward direction voltage initiationtime t₄, the diode 12 is turned on to maintain the reverse gate currenti.sub. gr as it gradually decreases. Thus, the reverse current havingthe waveform B of FIG. 9b can be confirmed until the time t₆. As statedabove, the gate reverse-bias can be effectively attained and the gatereverse-bias means can be simplified. Moreover, in the case of FIG. 8,the anode reverse-bias voltage V₃ gradually increases in a forwarddirection as shown in FIG. 9a whereby the satisfactory turn-off effectcan be attained even though the diode 12 is detected. That is, in thereverse gate current i_(gr) as shown in FIG. 9b by the dotted line A,the reverse gate current is maintained until the time the maximumforward voltage is reached at t₅ so that the period t₄ - t₅ can beprolonged as desired.

FIG. 10 is a diagram of another embodiment of the invention. In thisembodiment, the anode reverse-bias means is used for both the firstreverse-bias means 7 and the gate reverse-bias pulse generating means 10in a manner similar to that of FIG. 8. However, the connection of thegate reverse-bias gate circuit 20 is slightly different from that ofFIG. 8. The series circuit of the diode 12a, the charging resistor 15and the capacitor 16 is connected in parallel to the thyristor 3. Theconnection of the charging resistor 15 and the capacitor 16 is connectedthrough the resistor 17 to the gate of thyristor 3. The chargingresistor 15 is to charge the capacitor 16 during the anode reverse-biasperiod of the thyristor 3 (t₂ - t₄) (FIG. 11, a and b). During the anodereverse-bias period, the capacitor 16 is charged to the polarity of FIG.10 and the gate reverse-bias is maintained by the charge until after theapplication of the anode forward voltage whereby a similar result can beattained as that of the former embodiment.

FIG. 12 is a simplified diagram for the embodiments of FIG. 8 and FIG.10. In FIG. 12, the reference 20 designates a reverse gate energystorage element to store energy by the input of the reverse directionterminal voltage of the thyristor 3, (integrating element of inductiveelement 11 or capacitor 16) so as to apply it to the gate of thyristor 3as the reverse-bias. The reference IN designates an input terminal; OUTdesignates an output terminal and COM designates an input and outputcommon terminal.

FIGS. 13 and 14 are respectively diagrams of other embodiments of theinvention wherein the anode reverse-current pulse is also used as thegate reverse-bias pulse generating means 10 in the case using the anodereverse-bias means 7 by the pulse current.

The embodiment of FIG. 13 will now be described. In this embodiment, thediode 31 is connected in reverse parallel to the thyristor 3. In thefirst reverse-bias means 7, the series circuit of the capacitor 4b, thereactor 14 and the anode reverse-bias switch (thyristor) 5 is connectedin parallel to the thyristor 3. The diode 13 is connected in reverseparallel to the anode reverse-bias switch 5. On the other hand, the gatereverse-bias gate circuit 20 comprises the pulse current transformer 18,the diode 12 and the inductive element 11. The pulse current transformer18 is disposed between the branches of the anode reverse-current pass.One end of the secondary winding of the transformer is directlyconnected to the cathode of thyristor 3. The other end of the secondarywinding of the transformer is connected through the diode 12 to thecathode of thyristor 3. The inductive element 11 is connected betweenthe anode of diode 12 and the gate of thyristor 3.

In FIG. 13, as stated above, the gate reverse-bias (discharge ofcarriers around the junction J₂ by the gate reverse-bias during theanode reverse-bias period and its blocking ability recovery effect) isimproved by the diode 31 whereby the gate reverse bias effect (reversebiasing of the junction J₂ by the gate reverse-bias) is not permitted tobe disturbed by the anode reverse-bias. In the anode reverse-bias means,that is, the first reverse-bias means 7, the reactor 14 is connected inseries to the capacitor 7 at the time the anode reverse-bias switch 6 isturned on to give a ringing operation. The diode 31 connected in reverseparallel to the thyristor 3 is biased by the resonance pulse currenti_(p).

At this time, the pulse voltage V₁₀ in the polarity of FIG. 13 isgenerated by the pulse current transformer 18 in the output side of thepulse current transformer 18. In a manner similar to the embodiment ofFIG. 8, the gate reverse-bias performance is realized.

On the other hand, in the embodiment of FIG. 14, the first reverse-biasmeans of the series circuit of the reactor 14, the anode reverse-biasswitch (diode) and the capacitor 4b is connected in parallel to thethyristor 3. The thyristor 13a is connected in reverse parallel to theanode reverse-bias switch 5 instead of the diode 13 of FIG. 13. The gatereverse-bias gate circuit 20 comprises resistors 15, 17, capacitor 19and pulse current transformer 18. The resistor 17 and the capacitor 19are connected in series between the gate and cathode of the thyristor 3.The output side of the pulse current transformer 18 is connected throughthe resistor 15 in parallel to the capacitor 19. The pulse currenttransformer 18 is disposed between the cathode of thyristor 3 and thecapacitor 4b. As shown in FIG. 14, the capacitor 19 is used as thereverse-gate energy storage element. This feature is only different fromthat of FIG. 13.

In the embodiments of FIG. 13 and FIG. 14, the pulse current transformer18 functions to obtain the gate reverse-bias energy from the anodereverse-bias means instead of the diode 12a of the embodiment of FIG.10. The simplified diagram thereof is shown in FIG. 15. In FIG. 15, IN₁and IN₂ designate input terminals. The insulation between the input andthe output can be attained by using the pulse current transformer 18which can be inserted in a desirable passage of the anode reverse-biaspulse current loop.

FIG. 16 is a diagram of another embodiment of the invention wherein thepulse current transformer 18 itself is used as the gate reverse-biasenergy storage element.

The performance of the embodiment of FIG. 16 will be illustrated withreference to the performance waveforms of FIG. 17, a-c. As shown by thecurrent i₁₀₀ of FIG. 17a, the anode reverse-bias pulse current is passedto the first reverse-bias means 7. When the anode voltage of thyristor 3for the current is V₃ of FIG. 17a; and the magnetic core of the pulsecurrent transformer 18 is in the form of a reactor (mutual inductor),the induction voltage V_(10') of the secondary winding is as shown inFIG. 17b. That is, the energy is stored in the pulse current transformer18 during the period the anode reverse-bias pulse current i₁₀₀increases; the energy is discharged during the period the anodereverse-bias pulse current i₁₀₀ decreases, and the gate reverse-biaspulse voltage V_(10') is in reverse polarity to that of FIG. 16. Thevoltage is also stored through the diode 12a to the capacitor 19 wherebythe gate reverse-bias voltage V_(gr) is maintained as shown in FIG. 17ceven after extinction of the anode reverse-bias pulse current i₁₀₀.Thus, the embodiment of FIG. 16 attains the result of the invention.

FIG. 18 is a diagram of one embodiment of an inverter to which theinvention is applied and is one application of the embodiment of FIG. 8.In FIG. 18, the references 2a, 2b designate loads such as primarywindings of output transformers having a tap and 4b designates acapacitor for turn-off which is used for both of main thyristors 3a, 3b.The other thyristor 3a or 3b is used for the anode reverse-bias switch5a or 5b. In FIG. 18, as shown by the dotted line, the diodes 31a, 31bare connected in reverse parallel to the thyristors 3a, 3b and thecapacitor 4b and the reactors 14a, 14b are connected in series betweenboth anodes of thyristors 3a, 3b.

In FIG. 18, the embodiment can be modified to the reverse-bias method.In this case, when the thyristor 3a is turned off, the capacitor 4bhaving the polarity of FIG. 18 is discharged through the thyristor 3b topass the reverse-bias pulse current to the diode 31a in reverse parallelconnection. In this case, the voltage is applied to the reactor 14a inthe polarity of FIG. 18. The potential of the cathode of diode 12a₁ islower than the potential of the cathode of thyristor 3a in the degree ofthe applied voltage. During this period, the gate reverse-bias energy isaccumulated in the induction element 11a and the gate reverse-bias isinitiated. The gate reverse-bias continues to gradually decrease throughthe diode 12 even after extinction of the anode reverse-bias pulse. Theembodiment can be modified with various singal phase and multi-phaseinverters.

FIG. 19 is a diagram of another embodiment of the invention wherein twomain thyristors 3a, 3b are connected in series to form a basic circuitfor complimentary commutation between the thyristors 3a, 3b. In FIG. 19,the diodes 31a, 31b are connected to the partial windings T_(1a), T_(1b)of the commutation pulse transformer whereby the anode reverse-biasvoltages of the thyristors 3a, 3b are controlled to lower the voltage soas to effectively discharge the carriers around the junction J₂ by thegate reverse-bias and to charge directly from the diodes 12a₁, 12a₂ tothe capacitors 19a, 19b in the gate reverse-bias energy accumulation andto directly realize the gate reverse-bias for the voltage. The gatereverse-bias means can be simplified by this embodiment.

In FIG. 19, the reference D₁ designates a diode for controlling theincrease of the forward direction reapplying voltage in the thyristors3a, 3b by imparting a reverse voltage after actuation of the commutationpulse transformer T₁. In accordance with the invention, the gatereverse-bias is applied for a specific period after the anodereverse-bias until after the forward-bias initiation time. The forwardvoltage blocking in the remaining carriers can be attained whereby theturn-off period can be remarkably shortened. Accordingly, the turn-offmeans can be simplified.

The diode is outwardly connected or internally connected as IC inreverse parallel to the main thyristor whereby the discharge of carriersaround the middle junction J₂ by the gate reverse-bias, that is, theturn-off operation, can be effectively performed. Also, the gatereverse-bias is applied until after the anode forward bias initiationtime. The gate reverse-bias is gradually decreased whereby the gatereverse-bias can correspond to the condition of a decrease of theremaining amount of carriers of the thyristor, the injection carriersremain and the continuation of forward direction leakage and forwarddirection loss can be attained by an excess of reverse-gate currentcontinuation.

The breakover of the thyristor can be prevented by suddenly stopping thereverse gate current from the condition of excess reverse gate currentand the high reverse gate bias power which is remarkably higher thanthat of the turn-on gate. A loss thereof can be greatly decreased.Accordingly, the loss of thyristor and the gate circuit can be decreasedand the simplification of the reverse-gate circuit can be attained.Moreover, the gate reverse-bias energy accumulating element foraccumulating the anode reverse-bias power given from the anodereverse-bias means is provided so as to attain the gate reverse-biaswhereby the reverse gate bias means can be further simplified as well asthe above-mentioned results.

The induction element is connected in series to the gate electrode andthe diode is connected in reverse parallel to the input terminal of theinduction element in reverse polarity to the gate reverse-bias pulsevoltage. Accordingly, a similar result can be attained by the simplereverse gate bias circuit by applying the reverse gate bias pulsevoltage between the input terminals of the induction element.Accordingly, the power consumption for the reverse gate bias can bedecreased.

Moreover, needless gate reverse-bias during the anode reverse recovery-period (reverse current period) can be eliminated by delaying the gatereverse-bias period after the anode reverse-bias period whereby theturn-off of the thyristor is effectively attained, the gate reverse-biaspower consumption can be decreased and the switching loss advantageouslydecreased.

Obviously, numerous modifications and variations of the presentinvention are possible in light of the above teachings. It is thereforeto be understood that within the scope of the appended claims theinvention may be practiced otherwise than as specifically describedherein.

What is claimed as new and desired to be secured by Letters Patent ofthe United States is:
 1. A high speed method of turning off a thyristorin the conducting state, said thyristor having at least an anode, acathode and a gate, comprising the steps of:applying a reverse-biasbetween the anode and cathode of said thyristor; applying a reverse-biasto the gate of said thyristor; applying a forward-bias between the anodeand cathode of said thyristor while continuing to apply the reverse-biasto the gate of said thyristor; and subsequently removing thereverse-bias from the gate of said thyristor.
 2. The high-speed methodof turning off a thyristor in the conducting state recited in claim 1including the step of:decreasing gradually the reverse-bias applied tothe gate of said thyristor subsequent to the step of applying aforward-bias between the anode and cathode of said thyristor.
 3. Thehigh-speed method of turning off a thyristor in the conducting staterecited in claim 1 including the step of:providing a low-resistance pathfor current flow from the cathode to the anode of said thyristor whileapplying the reverse-bias to the gate of said thyristor.
 4. A thyristorhigh speed turn-off system comprising:a thyristor having at least ananode, a cathode and a gate; first reverse-bias means for applyingreverse-bias voltage between the anode and cathode of said thyristor;and second reverse-bias means for applying reverse-bias to the gate ofsaid thyristor, said second reverse-bias means coupled to said firstreverse-bias means and including means for integrating the reverse-biasvoltage applied between the anode and cathode of said thyristor to applythe integrated voltage as reverse-bias to the gate.
 5. The thyristorhigh speed turn-off system according to claim 4 wherein said integratingmeans includes a capacitor.
 6. The thyristor high speed turn-off systemaccording to claim 4 wherein said integrating means includes aninductive element.
 7. A thyristor high speed turn-off systemcomprising:a thyristor having at least an anode, a cathode and a gate; agate reverse-bias circuit including an inductive element and a diodeserially connected across the gate and the cathode of said thyristor;and gate reverse-bias pulse generating means connected in parallel tosaid diode of said gate reverse-bias circuit for applying reverse-biasvoltage pulses to the gate of said thyristor.